Publications
2026
Yilong Zhao, Fangxin Liu, Zongwu Wang, Mingjian Li, Mingxing Zhang, Chixiao Chen, and Li Jiang, BLADE: Boosting LLM Decoding’s Communication Efficiency in DRAM-based PIM, in Proceedings of the 31st Asia and South Pacific Design Automation Conference (ASP-DAC’26)
[slides]
2025
Yiwei Hu, Fangxin Liu, Zongwu Wang, Yilong Zhao, Tao Yang, and Li Jiang, PLAIN: Leveraging High Internal Bandwidth in PIM for Accelerating Large Language Model Inference via Mixed-Precision Quantization, in Proceedings of 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD’25)
Yilong Zhao, Fangxin Liu, Xiaoyao Liang, Mingyu Gao, Naifeng Jing, Chengyang Gu, Qidong Tang, Tao Yang, and Li Jiang, STAMP: Accelerating Second-order DNN Training Via ReRAM-based Processing-in-Memory Architecture, in Proceedings of the 16th International Symposium on Advanced Parallel Processing Technology (APPT’25)
Yilong Zhao, Mingyu Gao, Huanchen Zhang, Fangxin Liu, Gongye Chen, He Xian, Haibing Guan, and Li Jiang, PUSHtap: PIM-based In-Memory HTAP with Unified Data Storage Format, in Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3 (ASPLOS’25)
2024
Yilong Zhao, Mingyu Gao, Fangxin Liu, Yiwei Hu, Zongwu Wang, Han Lin, Ji Li, He Xian, Hanlin Dong, Tao Yang, Naifeng Jing, Xiaoyao Liang, and Li Jiang, UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space, in Proceedings of the 51st International Symposium on Computer Architecture (ISCA’24)
2023
Tao Yang, Hui Ma, Yilong Zhao, Fangxin Liu, Zhezhi He, Xiaoli Sun, and Li Jiang, PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy, in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE’23)
2022
Yilong Zhao, Li Jiang, Mingyu Gao, Naifeng Jing, Chengyang Gu, Qidong Tang, Fangxin Liu, Tao Yang, and Xiaoyao Liang, RePAST: A ReRAM-based PIM Accelerator for Second-order Training of DNN, arXiv preprint 2022
[arXiv]
Tao Yang, Fei Ma, Xiaoling Li, Fangxin Liu, Yilong Zhao, Zhezhi He, and Li Jiang, DTATrans: Leveraging dynamic token-based quantization with accuracy compensation mechanism for efficient transformer architecture, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022
Tao Yang, Dongyue Li, Fei Ma, Zhuoran Song, Yilong Zhao, Jiaxi Zhang, Fangxin Liu, and Li Jiang, Pasgcn: An reram-based pim design for gcn with adaptively sparsified graphs, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022
Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yilong Zhao, Tao Yang, Yiran Chen, and Li Jiang, IVQ: In-memory acceleration of DNN inference exploiting varied quantization, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022
2021
Tao Yang, Dongyue Li, Yibo Han, Yilong Zhao, Fangxin Liu, Xiaoyao Liang, Zhezhi He, and Li Jiang, PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration, in 2021 58th ACM/IEEE Design Automation Conference (DAC’21)
Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Yiran Chen, and Li Jiang, Bit-transformer: Transforming bit-level sparsity into higher preformance in ReRAM-based accelerator, in 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD’21)
Weidong Cao, Yilong Zhao(Co-First-Author), Adith Boloor, Yinhe Han, Xuan Zhang, and Li Jiang, Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals, in IEEE Transactions on Computers (TC), 2021
Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Tao Yang, Jingnai Feng, Xiaoyao Liang, and Li Jiang SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network, in 2021 IEEE 39th International Conference on Computer Design (ICCD’21)
Yilong Zhao, Zhezhi He, Naifeng Jing, Xiaoyao Liang, and Li Jiang. 2021. Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication. In Proceedings of the 2021 on Great Lakes Symposium on VLSI (GLSVLSI ‘21)
Tao Yang, Dongyue Li, Yibo Han, Yilong Zhao, Fangxin Liu, Xiaoyao Liang, Zhezhi He, Li Jiang, PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration, ACM/IEEE Design Automation Conference (DAC’21)
Ziqi Meng, Weikanu Oian, Yilong Zhao, Yanan Sun, Rui Yang, and Li Jiang, “Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation,” 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE’21)
Yanan Sun, Chang Ma, Zhi Li, Yilong Zhao, Jiachen Jiang, Weikang Qian, Rui Yang, Zhezhi He and Li Jiang, “Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2021
2020
Zhuoran Song, Yilong Zhao, Yanan Sun, Xiaoyao Liang and Li Jiang.ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory. Proceedings of the 2020 on Great Lakes Symposium on VLSI, (GLSVLSI’20)
Chaoqun Chu, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, Yunyan Hong, Xiaoyao Liang, Yinhe Han and Li Jiang. PIM-Prune: Fine-Grain DCNN pruning for Crossbar-based Process-In-Memory architecture. ACM/IEEE Design Automation Conference, (DAC’20)
Before 2019
Jia Wang, Yilong Zhao, Xin Huang and Guangqiang He. High Speed Polarization-Division Multiplexing Transmissions Based on the Nonlinear Fourier Transform, ZTE COMMUNICATIONS 17, 3 (2019).
Aiguo Sheng, Yilong Zhao, and Guangqiang He, “Characterization of Kerr Solitons in Microresonators with Parameter Optimization and Nonlinear Fourier Spectrum,” in Conference on Lasers and Electro-Optics, OSA Technical Digest (Optical Society of America, 2019), paper JW2A.47.
Aiguo Sheng, Yilong Zhao, and Guangqiang He, “Quadratic soliton combs in doubly resonant half-harmonic generation,” in Nonlinear Optics (NLO), OSA Technical Digest (Optical Society of America, 2019), paper NTu4A.18.
Patents
Fangxin Liu, Li Jiang, Yilong Zhao, “ Decoding acceleration methods, systems, devices, and readable storage media for large language models,” Application No. 2025118583915.5
Li Jiang, Yilong Zhao, “Reconfigurable Architecture, Accelerator,Circuit Deployment and Dataflow Methods,” Application No.202010910280.5, Authorization No. CN112181895B
Li Jiang, Yilong Zhao, Xiaosong Cui, Yun Chen, Jianxing Liao, “Neural Network Circuit,” Application No.202010729402.0, Authorization No. CN114004344A